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GAL20XV10
High-Speed E2CMOS PLD Generic Array LogicTM Features
* HIGH PERFORMANCE E2CMOS (R) TECHNOLOGY -- 10 ns Maximum Propagation Delay -- Fmax = 100 MHz -- 7 ns Maximum from Clock Input to Data Output -- TTL Compatible 16 mA Outputs -- UltraMOS(R) Advanced CMOS Technology * 50% to 75% REDUCTION IN POWER FROM BIPOLAR -- 90mA Maximum Icc -- 75mA Typical Icc * ACTIVE PULL-UPS ON ALL PINS * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100 ms) -- 20 Year Data Retention * TEN OUTPUT LOGIC MACROCELLS -- XOR Gate Capability on all Outputs -- Full Function and Parametric Compatibility with PAL12L10, 20L10, 20X10, 20X8, 20X4 -- Registered or Combinatorial with Polarity * PRELOAD AND POWER-ON RESET OF ALL REGISTERS * APPLICATIONS INCLUDE: -- High Speed Counters -- Graphics Processing -- Comparators * ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
4
OLMC
I/O/Q
I
4
OLMC
I
4
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE AND-ARRAY (40 X 40)
4
OLMC
I
I/O/Q
4
OLMC
I
I/O/Q
I
4
OLMC
I/O/Q
I
4
OLMC
I/O/Q
I
4
OLMC
I/O/Q
I
4
OLMC
I/O/Q
I
4
OLMC
I/O/Q
Description
The GAL20XV10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed Exclusive-OR PLD available in the market. At 90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides a substantial savings in power when compared to bipolar counterparts. E2CMOS technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20XV10 are the PAL(R) architectures listed in the macrocell description section of this document. The GAL20XV10 is capable of emulating these PAL architectures with full function and parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
I/OE
Pin Configuration
DIP PLCC
I/CLK
I/CLK I/O/Q Vcc I/O/Q
1
24
Vcc I/O/Q I/O/Q
I I
25 I/O/Q I/O/Q
I
I
NC
4 I I I NC I I I 11 12
I I
2
28
26
5
I I I I I I I I GND 12 6
GAL 20XV10
I/O/Q I/O/Q I/O/Q
7
GAL20XV10
Top View
14
GND NC
23
I/O/Q NC
9
21
I/O/Q I/O/Q
18
I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q
19 16
I/O/Q I/OE
I/O/Q
18
I/O/Q
13
I/OE
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
20xv10_02
1
Specifications GAL20XV10
GAL20XV10 Ordering Information
Commercial Grade Specifications
Tpd (ns)
10
Tsu (ns)
6
Tco (ns)
7
Icc (mA)
90
Ordering #
GAL20XV10B-10LP GAL20XV10B-10LJ
Package
24-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC
15
8
8
90
GAL20XV10B-15LP GAL20XV10B-15LJ
20
10
10
90
GAL20XV10B-20LP GAL20XV10B-20LJ
Part Number Description
XXXXXXXX _ XX XXX
GAL20XV10B
Device Name Grade Blank = Commercial
Speed (ns) L = Low Power Power
Package P = Plastic DIP J = PLCC
2
Specifications GAL20XV10
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the Output Logic Macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. The GAL20XV10 has two global architecture configurations that allow it to emulate PAL architectures. The Input mode emulates combinatorial PAL devices, with the I/CLK and I/OE pins used as inputs. The Feedback mode emulates registered PAL devices with the I/CLK pin used as the register clock and the I/OE pin as an output enable for all registers. The following is a list of PAL architectures that the GAL20XV10 can emulate. It also shows the global architecture mode used to emulate the PAL architecture. PAL Architectures Emulated by GAL20XV10 PAL12L10 PAL20L10 PAL20X10 PAL20X8 PAL20X4 GAL20XV10 Global OLMC Mode Input Mode Input Mode Feedback Mode Feedback Mode Feedback Mode Exclusive-OR macrocells. In Feedback mode, the state of the register is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the register is available to the AND array via an internal feedback path on macrocells 2 through 9 only, macrocells 1 and 10 have no feedback into the AND array. REGISTERED CONFIGURATION The Macrocell is set to Registered configuration when AC0 = 1 and AC1 = 0. Three of the four product terms are used as sum-ofproduct terms for the D input of the register. The inverting output buffer is enabled by the fourth product term. The output is enabled while this product term is true. The XOR bit controls the polarity of the output. The register is clocked by the low-to-high transition of the I/CLK. In Feedback mode, the state of the register is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the register is available to the AND array via an internal feedback path on macrocells 2 through 9 only, macrocells 1 and 10 have no feedback into the AND array. XOR COMBINATORIAL CONFIGURATION The Macrocell is set to the Exclusive-OR Combinatorial configuration when AC0 = 0 and AC1 = 1. The four product terms are segmented into two OR-sums of two product terms each, which are then combined by an Exclusive-OR gate and fed to an output buffer. The inverting output buffer is enabled by the I/OE pin, which is an active low output enable that is common to all XOR macrocells. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the I/O pin is available to the AND array via an input buffer path on macrocells 2 through 9 only, macrocells 1 and 10 have no input into the AND array. COMBINATORIAL CONFIGURATION The Macrocell is set to Combinatorial mode when AC0 = 1 and AC1 = 1. Three of the four product terms are used as sum-ofproduct terms for the combinatorial output. The XOR bit controls the polarity of the output. The inverting output buffer is enabled by the fourth product term. The output is enabled while this product term is true. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the I/O pin is available to the AND array via an input buffer path on macrocells 2 through 9 only, macrocells 1 and 10 have no input into the AND array.
INPUT MODE The Input mode architecture is defined when the global architecture bit SYN = 1. In this mode, the I/CLK pin becomes an input to the AND array and also provides the clock source for all registers. The I/OE pin becomes an input into the AND array and provides the output enable control for any macrocell configured as an Exclusive-OR function. Feedback into the AND array is provided from macrocells 2 through 9 only. In this mode, macrocells 1 and 10 have no feedback into the AND array. FEEDBACK MODE The Feedback mode architecture is defined when the global architecture bit SYN = 0. In this mode the I/CLK pin becomes a dedicated clock source for all registers. The I/OE pin is a dedicated output enable control for any macrocell configured as an Exclusive-OR function. The I/CLK and I/OE pins are not available to the AND array in this mode. Feedback into the AND array is provided on all macrocells 1 through 10. FEATURES Each Output Logic Macrocell has four possible logic function configurations controlled by architecture control bits AC0 and AC1. Four product terms are fed into each macrocell. XOR REGISTERED CONFIGURATION The Macrocell is set to the Exclusive-OR Registered configuration when AC0 = 0 and AC1 = 0. The four product terms are segmented into two OR-sums of two product terms each, which are then combined by an Exclusive-OR gate and fed into a D-type register. The register is clocked by the low-to-high transition of the I/CLK pin. The inverting output buffer is enabled by the I/OE pin, which is an active low output enable common to all
3
Specifications GAL20XV10
Input Mode
OE
D
Q
Q
XOR Registered Configuration - SYN = 1. - AC0 = 0. - AC1 = 0. - OLMC 1 and OLMC10 do not have the feedback path. - Pin 1(2) can be CLK and/or Input. - Pin 13(16) can be OE and/or Input.
CLK
D XOR
Q Q
Registered Configuration - SYN = 1. - AC0 = 1. - AC1 = 0. - XOR = 1 defines Active Low Output. - XOR = 0 defines Active High Output. - OLMC 1 and OLMC10 do not have the feedback path. - Pin 1(2) can be CLK and/or Input. - OE controlled by product term.
CLK
OE
XOR Combinatorial Configuration - SYN = 1. - AC0 = 0. - AC1 = 1. - OLMC 1 and OLMC10 do not have the feedback path. - Pin 13(16) can be OE and/or Input.
XOR
Combinatorial Configuration - SYN = 1. - AC0 = 1. - AC1 = 1. - XOR = 1 defines Active Low Output. - XOR = 0 defines Active High Output. - OLMC 1 and OLMC10 do not have the feedback path. - OE controlled by product term.
4
Specifications GAL20XV10
Input Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
0
0 120
4
8
12
16
20
24
28
32
36
OLMC
XOR - 1600 AC0 - 1610 AC1 - 1620
23(27)
2(3)
160 280
OLMC
XOR - 1601 AC0 - 1611 AC1 - 1621
22(26)
3(4)
320 440
OLMC
XOR - 1602 AC0 - 1612 AC1 - 1622
21(25)
4(5)
480 600
OLMC
XOR - 1603 AC0 - 1613 AC1 - 1623
20(24)
5(6)
640 760
OLMC
XOR - 1604 AC0 - 1614 AC1 - 1624
19(23)
6(7)
800 920
OLMC
XOR - 1605 AC0 - 1615 AC1 - 1625
18(21)
7(9)
960 1080
OLMC
XOR - 1606 AC0 - 1616 AC1 - 1626
17(20)
8(10)
1120 1240
OLMC
XOR - 1607 AC0 - 1617 AC1 - 1627
16(19)
9(11)
1280 1400
OLMC
XOR - 1608 AC0 - 1618 AC1 - 1628
15(18)
10(12)
1440 1560
OLMC
XOR - 1609 AC0 - 1619 AC1 - 1629
14(17)
11(13)
13(16)
40-USER ELECTRONIC SIGNATURE FUSES 1631, 1632, .... Byte4 Byte3 .... .... 1669, 1670 .... Byte1 Byte0 SYN - 1630
5
Specifications GAL20XV10
Feedback Mode
OE
D
Q
Q
XOR Registered Configuration - SYN = 0. - AC0 = 0. - AC1 = 0. - Dedicated CLK input on Pin 1(2). - Dedicated OE input on Pin 13(16).
CLK
D XOR
Q Q
CLK
Registered Configuration - SYN = 0. - AC0 = 1. - AC1 = 0. - XOR = 1 defines Active Low Output. - XOR = 0 defines Active High Output. - Dedicated CLK input on Pin 1(2). - OE controlled by product term. - Pin 13(16) is not connected to this configuration.
OE
XOR Combinatorial Configuration - SYN = 0. - AC0 = 0. - AC1 = 1. - Dedicated OE input on Pin 13(16). - Pin 1(2) is not connected to this configuration.
XOR
Combinatorial Configuration - SYN = 0. - AC0 = 1. - AC1 = 1. - XOR = 1 defines Active Low Output. - XOR = 0 defines Active High Output. - OE controlled by product term. - Both pin1(2) and pin 13(16) are not con nected to this configuration.
6
Specifications GAL20XV10
Feedback Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
0
0 120
4
8
12
16
20
24
28
32
36
OLMC
XOR - 1600 AC0 - 1610 AC1 - 1620
23(27)
2(3)
160 280
OLMC
XOR - 1601 AC0 - 1611 AC1 - 1621
22(26)
3(4)
320 440
OLMC
XOR - 1602 AC0 - 1612 AC1 - 1622
21(25)
4(5)
480 600
OLMC
XOR - 1603 AC0 - 1613 AC1 - 1623
20(24)
5(6)
640 760
OLMC
XOR - 1604 AC0 - 1614 AC1 - 1624
19(23)
6(7)
800 920
OLMC
XOR - 1605 AC0 - 1615 AC1 - 1625
18(21)
7(9)
960 1080
OLMC
XOR - 1606 AC0 - 1616 AC1 - 1626
17(20)
8(10)
1120 1240
OLMC
XOR - 1607 AC0 - 1617 AC1 - 1627
16(19)
9(11)
1280 1400
OLMC
XOR - 1608 AC0 - 1618 AC1 - 1628
15(18)
10(12)
1440 1560
OLMC
XOR - 1609 AC0 - 1619 AC1 - 1629
14(17)
11(13)
13(16)
40-USER ELECTRONIC SIGNATURE FUSES 1631, 1632, .... Byte4 Byte3 .... .... 1669, 1670 .... Byte1 Byte0 SYN - 1630
7
Specifications GAL20XV10
Absolute Maximum Ratings(1)
Supply voltage Vcc ....................................... -0.5 to+7V Input voltage applied .......................... -2.5 to VCC +1.0V Off-state output voltage applied ......... -2.5 to VCC +1.0V Storage Temperature ............................... -65 to 150C Ambient Temperature with Power Applied .......................................... -55 to 125C
1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN. VSS - 0.5 2.0 -- -- -- 2.4 -- -- -50 TYP.3 -- -- -- -- -- -- -- -- -- MAX. 0.8 VCC+1 -100 10 0.5 -- 16 -3.2 -150 UNITS V V A A V V mA mA mA
VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L -10/-15/-20
--
75
90
mA
1) The leakage current is due to the internal pull-up on all input and I/O pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at VCC = 5V and TA = 25 C
8
Specifications GAL20XV10
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAMETER COM COM
TEST COND.1 A A -- -- -- A
DESCRIPTION Input or I/O to Combinatorial Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled 3 2 -- 6 0 76.9 100 100 4 4 3 2 3 2
-10 MIN. MAX. 10 7 4 -- -- -- -- -- -- -- 10 9 9 9
-15 MIN. MAX. 3 2 -- 8 0 62.5 83.3 83.3 6 6 3 2 3 2 15 8 4 -- -- -- -- -- -- -- 15 10 15 10
-20 MIN. MAX. 3 2 -- 10 0 50 71.4 71.4 7 7 3 2 3 2 20 10 4 -- -- -- -- -- -- -- 20 15 20 15 UNITS ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns
tpd tco tcf2 tsu th
fmax3
A A
twh twl ten tdis
-- -- B B C C
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested
9
Specifications GAL20XV10
Switching Waveforms
INPUT or I/O FEEDBACK VALID INPUT
INPUT or I/O FEEDBACK
VALID INPUT
ts u
CLK
th
tpd
COMBINATORIAL OUTPUT
tc o
REGISTERED OUTPUT
Combinatorial Output
1/
fm a x
(external fdbk)
Registered Output
INPUT or I/O FEEDBACK
OE
tdis
OUTPUT
ten
OUTPUT
tdis
ten
Input or I/O Feedback to Enable/Disable
OE to Output Enable/Disable
tw h
CLK
1/
tw l
CLK 1/fmax (internal fdbk)
tcf
fm a x
(w/o fdbk)
REGISTERED FEEDBACK
tsu
Clock Width
fmax with Feedback
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Vcc
(Vref Typical = 3.2V)
Active Pull-up Circuit
Active Pull-up Circuit Tri-State Control Vcc
(Vref Typical = 3.2V)
Vref
Vcc
ESD Protection Circuit
Vref
Vcc
Data Output
PIN
PIN
ESD Protection Circuit
Feedback (To Input Buffer)
Typical Input
Typical Output
10
Specifications GAL20XV10
fmax Descriptions
CLK
LOGIC ARRAY
REGISTER
CLK
LOGIC ARRAY
tsu
tco
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
tcf tpd
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC ARRAY REGISTER
tsu + th
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT +5V
R1
3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 300 300 300 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
11
Specifications GAL20XV10
Electronic Signature
An electronic signature word is provided in every GAL20XV10 device. It contains 40 bits of reprogrammable memory that contains user defined data. Some uses include user ID codes, revision numbers, pattern identification or inventory control codes. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature bits, if programmed to any value other then zero(0) will alter the checksum of the device.
Latch-Up Protection
GAL20XV10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching.
Input Buffers
GAL20XV10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. GAL20XV10 input buffers have active pull-ups within their input structure. This pull-up will cause any un-terminated input or I/O to float to a TTL high (logical 1). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, Vcc, or GND. Doing this will tend to improve noise immunity and reduce Icc for the device. Typical Input Pull-up Characteristic
0
Input Current (A)
Security Cell
A security cell is provided in every GAL20XV10 device as a deterrent to unauthorized copying of the device pattern. Once programmed, this cell prevents further read access of the device pattern information. This cell can be only be reset by reprogramming the device. The original pattern can never be examined once this cell is programmed. The Electronic Signature is always available regardless of the security cell state.
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes less than a second. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
-20
-40 -60 0 1.0 2.0 3.0 4.0 5.0
Input Voltage (Volts)
Power-Up Reset
Circuitry within the GAL20XV10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asynchronous nature
Vcc (min.)
of system power-up, some conditions must be met to provide a valid power-up reset of the GAL20XV10. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Vcc
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
FEEDBACK/EXTERNAL OUTPUT REGISTER
Device Pin Reset to Logic "1"
12
Specifications GAL20XV10
Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
1.1
Normalized Tco
Normalized Tsu
PT H->L PT L->H
1
RISE 1.1 FALL
PT H->L
1.1
PT L->H
1
1
0.9
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tco
Normalized Tpd
Normalized Tsu
1.2 1.1 1 0.9 0.8 0.7 -55 -25
PT H->L PT L->H
1.2 1.1 1 0.9 0.8 0.7
RISE FALL
1.3 1.2 1.1 1 0.9 0.8 0.7
PT H->L PT L->H
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
Temperature (deg. C) Delta Tpd vs # of Outputs Switching
0
Temperature (deg. C)
Temperature (deg. C)
Delta Tco vs # of Outputs Switching
0
Delta Tpd (ns)
-0.5
Delta Tco (ns)
-0.5
-1
-1
RISE
-1.5
RISE
-1.5
FALL
-2 1 2 3 4 5 6 7 8 9 10
FALL
-2 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
12 10 12
Delta Tco vs Output Loading
RISE
10
RISE FALL
Delta Tpd (ns)
Delta Tco (ns)
8 6 4 2 0 -2 0 50
FALL
8 6 4 2 0 -2
100
150
200
250
300
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
13
Specifications GAL20XV10
Typical AC and DC Characteristic Diagrams
Vol vs Iol
3 2.5 5 4
Voh vs Ioh
4.5
Voh vs Ioh
4.25
Voh (V)
3 2 1 0
1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00
Voh (V)
10.00 20.00 30.00 40.00 50.00 60.00
Vol (V)
2
4
3.75
3.5 0.00 1.00 2.00 3.00 4.00
0.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.20 1.2
Normalized Icc vs Temp
1.70 1.60
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.10
1.1
Normalized Icc
1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70
1.00
1
0.90
0.9
0.80 4.50 4.75 5.00 5.25 5.50
0.8 -55 -25 0 25 50 75 100 125
0
25
50
75
100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
10
Input Clamp (Vik)
0 20
Delta Icc (mA)
8 6 4 2 0
Iik (mA)
40 60 80 100 120 -2.00 -1.50 -1.00 -0.50 0.00
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
Vik (V)
14

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